Seagate ST1.3 - Series 12 GB Hard Drive User's Guide

Porting MontaVista Linux to the XUP Virtex-II Pro Development Board Jonathon W. Donaldson Advisor: Prof. Warren R. Carithers Completed: Summer

Xilinx ChipScope Pro (optional) $700 8.1i Service Pack 3 Xilinx EDK $550 8.1i Service Pack 2 MentorGraphics® ModelSim DE/SE (optional) $2500 6.1e S

approximately half the cost of its ECC counterpart and much easier to find. The version that I used is available directly from Digilent’s website [23

6.2 Testing the Board The first step in working with a test board, which has been provided by another company or department, is to ensure that it is

In the next screen select the destination for the project directory and ensure that the location does not include any spaces and does not reside on a

Figure 3: Choosing a Board On the next screen we will choose the hard core PowerPC processor rather than the soft core MicroBlaze processor. It is

Figure 4: Selecting the PPC The only thing to be changed in Figure 4 is the PPC’s operating frequency to 300.00MHz, but there is a lot of informatio

rising and falling edges of the clock) off of this reference clock thereby creating a 133MHz sampling rate. Figure 5: PPC Configuration 6.3.2 Confi

than using software interrupts) for faster performance. The OPB is for low-speed, low-utilization devices. The PLB is for high-speed, high-performan

Figure 7: Ethernet_MAC and SysACE Configuration6 Figure 8 shows the external DDR memory configuration. Choose whatever memory size and rank matches

3) Modify Xilinx’s controller to support 64-bit 4) Write one own from scratch If the interrupt line is enabled by mistake when the system is built,

ABSTRACT Open source software and hardware create the perfect union when designing for an embedded system. Open source allows a developer to mold

Figure 9: PLB BRAM IF Controller Figure 10: STDIN/STDOUT Configuration The final page shown in Figure 11 provides a summary of the entire system.

Figure 11: Summary Window Now that we have the hardware configuration summary we can manually generate a graphical address map. The hardware addres

Remember, we have only told Xilinx what we would like it to create for us - we haven’t actually instantiated any part of the design yet. Before we do

Figure 13: OS and Library Configuration Click OK to any open child windows and then click on the Applications tab in the main XPS window and verify

Figure 14: Enabling the Boot Loop We are finally ready to start building something useful. Select the Hardware menu and click “Generate Bitstream”.

6.4 Creating the Cross-Compiler Environment At this point Xilinx has pretty much done all of the automation it can do for us. We now need to create

keep a constant eye on progress in a different screen session by using the ‘less’ command on the log file and hitting Shift+G. Or we can simply keep

zImage-EMBEDDED: zvmlinux cp zvmlinux ../images/zImage.$(END) In addition, the Xilinx BSP provides us with new OCP FIFO drivers for the system bu

The compilation process for the minimum kernel configuration took less than one minute on a 1.7GHz AMD Sempron with 512MB of memory. The resulting k

-hw implementation/system.bit -elf MontaVista_ELF/zImage.elf -ace MontaVista_ACE/system.ace Now, copy “<EDK_install_dir>/data/xmd/genace.tcl

TABLE OF CONTENTS ABSTRACT...

$ sudo mkdosfs –v –F 16 –R 1 -s 16 –n XLNX_ACE /dev/sdb1 Command to format partition 1 on Windows (drive letter may differ): C:\> mkdosfs –v –

2) Creates all directories needed for a usable file system 3) Copies PPC cross-compiled GLibc to RFS 4) Copies over the ‘/etc’ configuration files

This modification is the most important as it allows the kernel to treat the Xilinx SystemACE flash card as a block device (i.e. a storage device tha

But the above message cannot be displayed until we have a ‘/dev/console’ and the attempted print to STDOUT results in the following crash and ultimate

Basic support for process execution and dynamic kernel control is also displayed in the “General Setup” menu. These three options are not required f

First, add the following capabilities to the MontaVista kernel: Networking options ---> [*] Packet socket [*] Unix domain sockets [*] T

For the micro-DHCP client we need to create some simple scripts. These scripts can be found in the ‘/etc’ directory available on my website [2] or si

Configure BusyBox with the httpd daemon: Networking Utilities ---> [*] httpd Add the following to the ‘/etc/inetd.conf’ file (my ‘mkrootfs.

6.13 Booting Linux via NFS (Future Work) This will require an NFS server and NFS support to be configured in the kernel. 6.14 Booting Linux Kernel

As it turns out there is one key setting within the XPS application development tab regarding what is called the “boot loop”. The Xilinx boot loop a

8.1 ECC MEMORY... 44 8.2

Clearly, the compiler decided to completely disregard my loop (a.k.a. the compiler writer telling the programmer they are inferior ☺) and only ever ch

could not attach itself to the virtual terminal in ‘/dev/tts’. If there is no terminal with which to accept user input then there is also no point in

I booted the board and when the ‘init’ process started it ran the startup script that I wrote from scratch perfectly, but as soon as it attempted to

I also thought that it might be a permissions issue in the root file system so I tried different combinations of the following commands but none of t

What I still didn't understand is why ‘vi’ wasn't displaying the ‘^M’ characters in the file. After doing some research online it turned o

An ECC memory module is identifiable by simply counting the number of chips on the memory module. If the number of chips is odd then it is ECC memory

Figure 15: How ranks can be applied to a DIMM [46] There are currently three different types of ranked memory: single, dual, and quad. Memory modul

DDR memory differs from SDR memory in that data is transferred on every clock edge. This is accomplished by giving the memory module an internal data

For more information on DDR memory and its functionality please refer to the following functional specification provided by Micron [54]. 8.4 Linux Bo

Interrupt Controller remapping: Xilinx INTC #0 at 0x41200000 mapped to 0xFDFFE000 UART_16550A remapping: ttyS00 at 0xfdfff003 (irq = 29) is a 165

LIST OF ILLUSTRATIONS Figures FIGURE 1: THE BSB WIZARD...

1) ‘getty’ – used to bring up a login prompt 2) The program to be executed when “Ctrl-Alt-Delete” is pressed (e.g. “shutdown –r now”) Steps 1-5 of

If a designer intends to create a proprietary design when using open source code it is important to know the major differences between BSD and GNU lic

Figure 16: IBM CoreConnect™ Bus Architecture [59] Xilinx supports the CoreConnect bus architecture on both the soft core MicroBlaze™ processor and t

17). The x86 implementation also requires the use of special I/O instructions (e.g. in, out) and a port address register (i.e. DX). Figure 17: 8086

The work that Xilinx goes through to generate the bit stream for the design (hopefully within the timing constraints) that is ultimately mapped to the

be significant! Therefore, the PAR algorithms are the final determining factor in whether or not the user’s design will meet the timing constraints g

ACE file have been uploaded to the FPGA, SystemACE uploads the ELF kernel image contents of the ACE file to SDRAM. Please refer to the sections in th

0x0020 Auto-negotiation complete 0x0010 Remote fault 0x0008 Capable of Auto-negotiation 0x0004 Link established 0x0002 Jabber detected 0x0001 Extended

10 Conclusion The Xilinx and Digilent websites provide myriad documents and training information for novice and expert embedded systems designers a

[4] Lin. J.. Jamie’s Research @ WSU. http://www.eecs.wsu.edu/~jamie/. May 2006. [5] Van Essen. B. C. UW CSE Homepage. http://www.cs.washington

1 Disclaimer If you “let the smoke out” or otherwise ruin the development board while working through this document I take no responsibility - conti

[20] Rochester Institute of Technology. College of Applied Science and Technology. http://www.rit.edu/~700www/. August 2006. [21] Rochester Insti

[35] BitMover Inc.. http://www.bitkeeper.com/. August 2006. [36] Xilinx Inc.. Generating ACE File in EDK. ftp://ftp.xilinx.com/pub/documentation/m

[49] Xilinx Inc.. Xilinx XUP Virtex-II Pro Development System: Supported DIMM Modules. http://www.xilinx.com/univ/xupv2p_supported_dimms.html. Augu

[63] Altera Corp.. Jitter Comparison Analysis. http://www.altera.com/literature/tb/tb70.pdf. January 2001. [64] Saleh. R.. Flip-Flop and Clock D

[79] Sun Microsystems. Solaris 9 Operating Environment. http://www.sun.com/software/solaris. August 2006. [80] The Eclipse Foundation. http://w

Appendix A.1 Minimum Kernel Configuration w/o RFS Below are the minimum (i.e. anything not listed here may be disabled) kernel configuration options

Now booting the kernel Linux version 2.4.26 (jwdonal@terranova) (gcc version 3.4.4) #52 Thu Aug 3 23:15:34 MDT 2006 Xilinx Virtex-II Pro port (C) 2002

Login/Password Management Utilities ---> [*] getty [*] login Shells ---> Choose your default shell (ash) ---> --- ash If using

…string: "console=ttyS0,9600 root=/dev/xsysace/disc0/part3 rw" Block devices ---> [*] Xilinx on-chip System ACE Character

POSIX conformance testing by UNIFIX Linux NET4.0 for Linux 2.4 Based upon Swansea University Computer Society NET3.039 Starting kswapd devfs: v1.12c (

The two major components of this study are to first create an embedded hardware system and then integrate a unique software operating system which uti

NCD – contains all necessary information to implement the design on the specified device (V2P, CR-II, etc). BIT – this file is simply a compilation o

A.7 Block Diagram 71

A.8 Memory Map 0x0FFFFFFF0x000000000x1FFFFFFF0x100000000x7FFFFFFF0x40000000UNUSED(2GB - 128KB)0xFFFFFFFF0xFFFE0000PLB-to-OPBBridge(1GB)Devices:System

A.9 Acronyms Acronym Decode ACE Adaptive Configuration Environment AGP Accelerated Graphics Port AHB Advanced High-performance Bus ALU Arithmetic Lo

DMAC DMA Controller DNU Do Not Use DOS Disk Operating System DRAM Dynamic Random Access Memory ECC Error-Correction Code EDIF Electronic Data Inte

IDE Integrated Development Environment IIC Inter-Integrated Circuit IP Intellectual Property IP Internet Protocol IPC Intel Process Communications I

OS Operating System PACE Pinout and Area Constraints Editor PAO Peripheral Analysis Order PAR Place and Route PC4 PCIV PCB Printed Circuit Board P

SSH Secure SHell SSTL Stub Series Terminated Logic SVF Serial Vector Format TCL Tool Command Language (µPC Driver Command) TLA Top Level Aggregator

5 Motivation In August of 2005 the Department of Defense and OMB issued a memorandum [77] stating that all U.S. government agencies must be IPv6 co

In the most general case, porting an RTOS to the Xilinx V2P or V4FX development boards consists of the following steps: 1) Acquire the preliminary h