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Parallel SCSI Interface Product Manual, Rev. A 55
4. If the SCSI initiator creates an attention condition, the SCSI target port shall go to a MESSAGE OUT
phase, receive all the message bytes, and cause an unexpected bus free by generating a BUS FREE
phase (see
Section 3.1.1.1 on page 51).
5. If the SCSI target port detects the SEL signal being true, the SCSI target port shall release the BSY,
MSG, C/D, and I/O signals within one QAS release delay.
6. After waiting at least one QAS arbitration delay from negating the SCSI MSG, C/D, and I/O signals in
step 2, if there are no SCSI ID bits true, the SCSI target port shall transition to the BUS FREE phase.
7. After waiting at least one QAS arbitration delay from negating the MSG, C/D, and I/O signals in step 2, if
there are any SCSI ID bits true, the SCSI target port shall wait at least a second QAS arbitration delay. If
the SEL signal is not true by the end of the second QAS arbitration delay, the SCSI target port shall tran
-
sition to the BUS FREE phase.
Note. The release of MSG, C/D, and I/O may cause release glitches. Step 5 above ensures these glitches
occur at a time when no connection is established on the bus so that they do not interfere with proper
operation.
The procedure for a SCSI device with QAS enabled to obtain control of the SCSI bus via QAS is as follows:
1. The SCSI device shall first wait for MESSAGE IN phase to occur with a single QAS REQUEST mes-
sage. When the SCSI device detects the ACK signal being false for the QAS REQUEST message and
the attention condition is cleared, it shall begin the QAS phase.
2. The SCSI device shall wait a minimum of a two system deskew delays after detection of the MSG, C/D,
and I/O signals being false before driving any signal.
3. Following the delay in step 2, the SCSI device may arbitrate for the SCSI bus by asserting its own SCSI
ID within one QAS assertion delay from detection of the MSG, C/D, and I/O signals being false. If arbitra-
tion fairness is enabled, the SCSI device shall not arbitrate until its fairness register is cleared.
4. After waiting at least one QAS arbitration delay, measured from the detection of the MSG, C/D, and I/O
signals being negated, the SCSI device shall examine the Data Bus.
a. If no higher priority SCSI ID bit is true on the Data Bus and the fairness algorithm allowed the SCSI
device to participate, then the SCSI device has won the arbitration and it shall assert the SEL signal.
b. If a higher priority SCSI ID bit is true on the Data Bus (see Table 1 for the SCSI ID arbitration priorities) or
the fairness algorithm (see Section 3.4) prevented the SCSI device from participating in QAS arbitration,
then the SCSI device has lost the arbitration.
c. Any SCSI device other than the winner has lost the arbitration and shall release its SCSI ID bit after two
system deskew delays and within one QAS release delay after detection of the SEL signal being asserted.
A SCSI device that loses arbitration may return to step
1.
5. The SCSI device that wins arbitration shall wait at least a QAS arbitration delay after asserting the SEL
signal before changing any signals.
6. After the QAS arbitration delay in step 4, SCSI devices with arbitration fairness enabled that are not arbi-
trating shall start sampling the Data Bus to determine the SCSI devices that are attempting arbitration,
the SCSI device that won, and the SCSI devices that lost. This sampling shall continue for one bus settle
delay plus two system deskew delays. The SCSI devices shall update their fairness register with all
device IDs that lost arbitration.
The SCSI ID bit is a single bit on the Data Bus that corresponds to the SCSI device’s unique SCSI address. All
other Data Bus bits shall be released by the SCSI device. The DB(P_CRCA) and DB(P1) are not valid during
the QAS phase. During the QAS phase, DB(P_CRCA), and DB(P1) may be released or asserted, but shall not
be actively driven false.
3.2 SELECTION phase
The SELECTION phase allows a SCSI initiator port to select a SCSI target port for the purpose of initiating
some target function (e.g., READ or WRITE command). During the SELECTION phase, the I/O signal is
negated to distinguish this phase from the RESELECTION phase.
- Parallel SCSI Interface 1
- Revision status summary sheet 5
- Table of Contents 7
- List of Figures 13
- 1.0 Interface requirements 15
- standards 16
- 1.4 Summary of SCSI messages 26
- 2.0 SCSI bus 27
- 2.1 SCSI bus signals overview 29
- 2.2 Signal states 31
- 2.3 OR-tied signals 32
- 2.4 Signal sources 33
- 2.5 SCSI bus timing 34
- 0 0.5 0 0.2 39
- induced time asymmetry 39
- due to resis 43
- 2.6 Measurement points 47
- 2.9 Data transfer modes 51
- 2.12 Negotiation 53
- PPR, SDTR Less than or equal 55
- 2.12.4 Transfer agreements 56
- Table 13: Transfer agreements 56
- bit shall be set to zero 61
- Transfer 62
- 3.0 Logical characteristics 65
- 3.2 SELECTION phase 69
- 3.3 RESELECTION phase 72
- 3.4 SCSI bus fairness 73
- 3.6 COMMAND phase 89
- 3.7 DATA phase 89
- 3.8 STATUS phase 90
- 3.9 MESSAGE phase 90
- 3.11 SCSI bus phase sequences 92
- 3.12 Data bus protection 95
- 4.2 Message formats 97
- 4.3 Message categories 99
- 7 6 5 4 3 2 1 0 101
- 0 IDENTIFY DISCPRIV LUN 101
- Target’s Parallel Protocol 109
- 4.4 Task attribute messages 116
- 4.5 Task management messages 119
- 5.1 Attention condition 121
- 5.2 Bus reset condition 122
- 5.3 Hard reset 122
- 5.4 Reset events 123
- 6.0 SPI information units 127
- [3] See Figure 16 129
- [4] See Figure 18 129
- [3] See Figure 18 130
- 6.2 SPI information units 132
- field shall be reserved 135
- field is not zero 135
- 129 143
- 7.0 SCSI commands 145
- See notes following Table 61 148
- 7.3 Status 152
- 7.4 Command examples 154
- 7.5 Timing examples 156
- 7.8 Parameter rounding 163
- 8.0 Drive features 165
- Command, Message, and Status 168
- (Bits 14 171
- Seagate Technology LLC 186
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